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1 of 30 march 3, 2005 ? 2005 integrated device technology, inc. *notice: the information in this document is subject to change without notice dsc 6797 idt and the idt logo are trademarks of integrated device technology, inc. description description description description the 89TTM553 is a flow-based traffic management co-processor that can be used in conjunction with the 89ttm552. it has two major functional parts: the queue manager (qm) and the flq scheduler. the qm is responsible for all the non-bandwidth func- tions, which include managing up to 1 million queuing structures, handling cell and packet arrivals and departures from these queues, and maintaining a database of congestion management and statistics parameters for each flow queue (flq). the flq scheduler is respon- sible for managing the flq bandwidth functions. the 89TTM553 flq scheduler supports traffic scheduling on up to 1m discrete flows. in addition to the scheduling levels provided by the 89ttm552, the 89TTM553 provides one or two levels of additional scheduling hierarchy. it also provides guaranteed minimum rate, maximum rate capping, excess rate distribution using weighted fair queuing (wfq), byte rate shaping, and dynamic configuration adjust- ments. the 89TTM553 stores all the flow-based parameters (and state infor- mation) that are made available to the 89ttm552 for flow-based processing. when the 89TTM553 is used with the 89ttm552, conges- tion and bandwidth management features are enabled at the flow level as well as at the aggregate-flow level. 89ttm55x f 89ttm55x f 89ttm55x f 89ttm55x features eatures eatures eatures deterministic performance at 10 gbps wire-speed (35 mcps) regardless of the number of flows, traffic size, and patterns. up to 256 megabytes of external memory buffer space (equivalent to a 210 ms buffer at 10 gbps). support (rx and tx) for industry-standard spi-4 phase 2, npf streaming interface, and csix over lvds. hierarchical queuing and precise scheduling: ? traffic management flexibility. ? support for up to 4k aggregate flow queues (afqs), 1k port queues (pqs), 2k arrival reassembly queues (arqs), and 1k output queues/channels (oqs) with no external memory required. configurable afq-to-port assignments. ? support for up to 1m discrete flows (flqs), with queuing for each flow, using external memory. configurable mapping of flqs into aggregate flow queues. ? two-level flq scheduling mode that supports up to 128k or 256k virtual pipe or subscriber queues with up to 8 or 4 cos priority queues each. ? accurate byte-rate shaping at the flq, afq and port levels. multiple levels of buffer congestion management. ? hierarchical queue structure and thresholding. ? congestion indication. ? dynamic adjustment of thresholds during periods of congestion. ? packet discard (pd). ? weighted random early discard (wred). ? local congestion indication (ci). 89TTM553 preliminary information* traffic manager co-processor data sheet
2 of 30 march 3, 2005 idt 89TTM553 configurable forwarding based on classification index. two ports for obtaining event-based statistics. configurable on-chip diagnostic statistics. bandwidth management rate guarantee and shaping mechanisms for each flow, each aggregate flow and each port queue. ? priority and weighted bandwidth distribution mechanisms across groups of flows and aggregate flows. ? schedules rates as low as 2 kbps for each flow. ? one- and two-level byte-rate flq scheduling: maximum and minimum rates, and strict priority and weighted fair queuing (wfq) fo r each flq. per-flow byte-rate shaping. ? afq scheduling with byte-rate shaping: minimum and maximum rates with vbr mbs and pcr enforcement. excess distribution using weighted fair queuing (wfq) and prr. ? port queues: maximum rates with byte-rate scheduling. wire-speed logical multicasting. ? four classes of service. ? programmable service rate (minimum and excess bandwidth distribution). ? programmable thresholds. ? branch connections can be added and deleted during live traffic. ? traffic management features on all multicast roots and branches. multicast label generation for spatial multicast support. integrated wire-speed aal-5 segmentation and reassembly (aal-5 cpcs sar) in the datapath. 32-bit processor interface running at up to 66 mhz with integrated aal-5 sar and dma engine for data insertion and extraction. ? four classes of service. ? integrated aal-5-compliant and packet-based sar. ? programmable service rate. ? programmable queue thresholds. ? use of descriptors and dma support for maximum performance. ? 16-bit data bus transfer at up to 66 mhz. algorithms implemented in hardware; software intervention required for initialization and configuration only. error protection on all external ram and bist on all internal ram. inter-operable with the idt ztm200 traffic manager.
3 of 30 march 3, 2005 idt 89TTM553 8 8 8 89ttm55x functional block diagram 9ttm55x functional block diagram 9ttm55x functional block diagram 9ttm55x functional block diagram cpu and peripheral interface (cpif, dma) queue manager (qm) control path sar (sar) multicast engine (dfc) memory controller (pbc) dst, btx dsr, brx forwarding and thresholding engine (ac) queue manager (qm) packet scheduler (ss) statistics processor (sp) external statistics port data buffer memory (ddr sdram) spi-4.2 or streaming interface or s ix-over-lvds spi-4.2 or streaming interface or csix-over-lvd datapath aal-5 sar (ils) extended scheduler interface 89ttm552 89TTM553 packet scheduler (ars, gs, wfq) 89ttm552-to-89TTM553 interface zbus tx rx oq manager (voqm, bpq) forwarding and thresholding engine (ac) statistics processor (sp) cpu and peripheral interface (cpif, dma) zbus
4 of 30 march 3, 2005 idt 89TTM553 89TTM553 pin description 89TTM553 pin description 89TTM553 pin description 89TTM553 pin description note: information in this section is subject to change. contact your idt fae before making design decisions. in this data sheet, direction is indicated as follows: i for in, o for out, b for bi-directional, and p for power. signal name i/o type dir. freq. remarks bll_clk_cp, bll_clk_cn 1.5v hstl class 1 i 175 mhz bll qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. bll_clk_kp, bll_clk_kn 1.5v hstl class 1 o 175 mhz bll qdr sram output clock: this clock pair times the control outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. bll_addr[21:0] 1.5v hstl class 1 o 175 mhz bll qdr sram address outputs. bll_rd_n 1.5v hstl class 1 o 175 mhz bll qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. bll_din[17:0] 1.5v hstl class 1 i 175 mhz bll qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations bll_wr_n 1.5v hstl class 1 o 175 mhz bll qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. bll_dout[17:0] 1.5v hstl class 1 o 175 mhz bll qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations bll_vref 0.75v ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v table 1 buffer linked list qdr sram signal name i/o type dir. freq. remarks bxt_clk_cp, bxt_clk_cn 1.5v hstl class 1 i 175 mhz bxt qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. bxt_clk_kp, bxt_clk_kn 1.5v hstl class 1 o 175 mhz bxt qdr sram output clock: this clock pair times the con- trol outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. bxt_addr[21:0] 1.5v hstl class 1 o 175 mhz bxt qdr sram address outputs. bxt_rd_n 1.5v hstl class 1 o 175 mhz bxt qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. bxt_din[3:0] 1.5v hstl class 1 i 175 mhz bxt qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations table 2 buffer linked list extension qdr sram (part 1 of 2)
5 of 30 march 3, 2005 idt 89TTM553 bxt_wr_n 1.5v hstl class 1 o 175 mhz bxt qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. bxt_dout[3:0] 1.5v hstl class 1 o 175 mhz bxt qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations bxt_llt_vref 0.75v ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v signal name i/o type dir. freq. remarks fct_clk_cp, fct_clk_cn 1.5v hstl class 1 i 175 mhz fct qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. fct_clk_kp, fct_clk_kn 1.5v hstl class 1 o 175 mhz fct qdr sram output clock: this clock pair times the con- trol outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. fct_addr[19:0] 1.5v hstl class 1 o 175 mhz fct qdr sram address outputs. fct_rd_n 1.5v hstl class 1 o 175 mhz fct qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. fct_din[27:0] 1.5v hstl class 1 i 175 mhz fct qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations fct_wr_n 1.5v hstl class 1 o 175 mhz fct qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. fct_dout[27:0] 1.5v hstl class 1 o 175 mhz fct qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations fct_vref[1:0] 0.75 ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v table 3 flow control table qdr sram signal name i/o type dir. freq. remarks fpt_clk_cp, fpt_clk_cn 1.5v hstl class 1 i 175 mhz fpt qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. fpt_clk_kp, fpt_clk_kn 1.5v hstl class 1 o 175 mhz fpt qdr sram output clock: this clock pair times the con- trol outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. fpt_addr[20:0] 1.5v hstl class 1 o 175 mhz fpt qdr sram address outputs. fpt_rd_n 1.5v hstl class 1 o 175 mhz fpt qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. table 4 flow parameters table qdr sram (part 1 of 2) signal name i/o type dir. freq. remarks table 2 buffer linked list extension qdr sram (part 2 of 2)
6 of 30 march 3, 2005 idt 89TTM553 fpt_din[35:0] 1.5v hstl class 1 i 175 mhz fpt qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations fpt_wr_n 1.5v hstl class 1 o 175 mhz fpt qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. fpt_bw_n[3:0] 1.5v hstl class 1 o 175 mhz fpt qdr sram synchronous write byte enables (active low) fpt_dout[35:0] 1.5v hstl class 1 o 175 mhz fpt qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations fpt_vref[1:0] 0.75v ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v signal name i/o type dir. freq. remarks gpt_clk_cp, gpt_clk_cn 1.5v hstl class 1 i 175 mhz gpt qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. gpt_clk_kp, gpt_clk_kn 1.5v hstl class 1 o 175 mhz gpt qdr sram output clock: this clock pair times the con- trol outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. gpt_addr[20:0] 1.5v hstl class 1 o 175 mhz gpt qdr sram address outputs. gpt_rd_n 1.5v hstl class 1 o 175 mhz gpt qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. gpt_din[17:0] 1.5v hstl class 1 i 175 mhz gpt qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations. gpt_wr_n 1.5v hstl class 1 o 175 mhz gpt qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. gpt_bw_n[1:0] 1.5v hstl class 1 o 175 mhz gpt qdr sram synchronous byte enables (active low). gpt_dout[17:0] 1.5v hstl class 1 o 175 mhz gpt qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations. gpt_vref 0.75v ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v table 5 group parameters table qdr sram signal name i/o type dir. freq. remarks table 4 flow parameters table qdr sram (part 2 of 2)
7 of 30 march 3, 2005 idt 89TTM553 signal name i/o type dir. freq. remarks ht_clk_cp, ht_clk_cn 1.5v hstl class 1 i 175 mhz ht qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. ht_clk_kp, ht_clk_kn 1.5v hstl class 1 o 175 mhz ht qdr sram output clock: this clock pair times the control outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. ht_addr[19:0] 1.5v hstl class 1 o 175 mhz ht qdr sram address outputs. ht_rd_n 1.5v hstl class 1 o 175 mhz ht qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. ht_din[35:0] 1.5v hstl class 1 i 175 mhz ht qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations. ht_wr_n 1.5v hstl class 1 o 175 mhz ht qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. ht_dout[35:0] 1.5v hstl class 1 o 175 mhz ht qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations. ht_vref[1:0] 0.75v ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v table 6 head tail qdr sram signal name i/o type dir. freq. remarks llt_clk_cp, llt_clk_cn 1.5v hstl class 1 i 175 mhz llt qdr sram input clock: this clock pair registers data inputs on the rising edge of c and c#. all synchronous inputs must meet setup and hold times around the clock rising edges. llt_clk_kp, llt_clk_kn 1.5v hstl class 1 o 175 mhz llt qdr sram output clock: this clock pair times the control outputs to the rising edge of k, and times the address and data outputs to the rising edge of k and k#. llt_addr[19:0] 1.5v hstl class 1 o 175 mhz llt qdr sram address outputs. llt_rd_n 1.5v hstl class 1 o 175 mhz llt qdr sram synchronous read output (active low): when asserted, a read cycle is initiated to the external qdr sram devices. llt_din[10:0] 1.5v hstl class 1 i 175 mhz llt qdr sram data inputs: input data must meet setup and hold times around the rising edges of c and c# during read operations. llt_wr_n 1.5v hstl class 1 o 175 mhz llt qdr sram synchronous write output (active low): when asserted, a write cycle is initiated to the external qdr sram devices. llt_dout[10:0] 1.5v hstl class 1 o 175 mhz llt qdr sram write data outputs: output data is synchro- nized to the k and k# during write operations. table 7 linked list table qdr sram
8 of 30 march 3, 2005 idt 89TTM553 signal name i/o type dir. freq. remarks flqs_din[14:0] flqs_din_prty 1.5v hstl class 1 i 175 mhz control serial interface to 89ttm552 (15 signal lines + 1 parity line) flqs_dout[19:0] flqs_dout_prty 1.5v hstl class 1 o 175 mhz control serial interface to 89ttm552 (20 signal lines + 1 parity line) flqs_clkin 1.5v hstl class 1 i 175 mhz clock input from 89ttm552 flqs_clkout 1.5v hstl class 1 o 175 mhz clock output to 89ttm552 flqs_tic_in 1.5v hstl class 1 i 175 mhz cell time tic input from 89ttm552 flqs_tic_out 1.5v hstl class 1 o 175 mhz cell time tic out to 89ttm552 flqs_vref 0.75v ? ? hstl reference. nominally v ddq / 2, so connect to 0.75 v table 8 89ttm552/89TTM553 interface signal name i/o type dir. freq. remarks zbus_avalid_n 3.3v lvttl, 12ma drive, internal pullup b 33 or 66 mhz zbus address valid flag (active low) zbus_clk 3.3v, no internal pullup i 33 or 66 mhz zbus clock input (up to 66 mhz) zbus_ad[15:0] 3.3v lvttl, 12ma drive, internal pullup b 33 or 66 mhz zbus 16-bit multiplexed address/data bus zbus_devid[4:0] 3.3v, internal pullup i 33 or 66 mhz used for zbus device identification zbus_dvalid_n 3.3v lvttl, 12ma drive, internal pullup b 33 or 66 mhz zbus data valid flag (active low) zbus_gnt_n 3.3v, internal pullup i 33 or 66 mhz zbus grant (active low) zbus_int_n[2:0] 3.3v lvttl, 12ma drive o 33 or 66 mhz zbus device interrupt (active low) zbus_prty 3.3v lvttl, 12ma drive, internal pullup b 33 or 66 mhz zbus parity over address/data; one parity bit for 16 bits zbus_dir 3.3v lvttl, 12ma drive o 33 or 66 mhz zbus write/read flag zbus_req_n 3.3v lvttl, 12ma drive o 33 or 66 mhz zbus master cycle request (active low) table 9 processor interface (zbus)
9 of 30 march 3, 2005 idt 89TTM553 signal name i/o type dir. freq. remarks iddq 3.3v, internal pulldown i n/a iddq input (active high). for idt use only. do not connect. reserve_1 3.3v lvttl, 4 ma drive on/a for idt use only. do not connect. scan_en 3.3v i n/a scan enable (active high) for idt use only. attach to a 4.7k resistor to 0v reserve_0 3.3v, internal pullup i n/a tristate enable (active low) for idt use only. attach to a 4.7k resistor to 3.3v tck 3.3v i ? jtag (ieee 1149.1) clock input. tdi 3.3v, internal pullup i ? jtag (ieee 1149.1) test data input. tdo 3.3v lvttl, 12 ma drive o ? jtag (ieee 1149.1) test data output. tms 3.3v, internal pullup i ? jtag (ieee 1149.1) test mode select trst_n 3.3v, internal pullup i ? jtag (ieee 1149.1) test reset input. table 10 test i/o signal name i/o type dir. freq. remarks pll_2x_bpclk 3.3v, internal pulldown i n/a bypass clock input for idt use only. do not connect. pll_bp_mode 3.3v, internal pulldown i n/a bypass clock input for idt use only. do not connect. pll_mon 3.3v lvttl, 12ma drive o n/a pll monitor for idt use only. do not connect. pll_cfg_ovr 3.3v, internal pulldown i n/a pll configuration override pll_rst 3.3v i async pll reset. a special initialization sequence is required. pll_vdda 1.8v ? ? pll analog vdd pll_vssa ? ? ? pll analog vss pll_sys_refclk 3.3v i 100 mhz chip core pll reference clock. reset_n 3.3v, internal pullup i async chip reset input (active low). vdd18 ? ? ? 1.8v core power vdd15 ? ? ? 1.5v i/o power for hstl-2 i/os: isolated output buffer supply set nominally to 1.5v table 11 pll i/o (part 1 of 2)
10 of 30 march 3, 2005 idt 89TTM553 8 8 8 89TTM553 electrical specifications 9ttm553 electrical specifications 9ttm553 electrical specifications 9ttm553 electrical specifications some data are tbd and will be published as they become available. the specifications are subject to change without notice. a a a absolute maximum ratings bsolute maximum ratings bsolute maximum ratings bsolute maximum ratings the absolute maximum ratings are the maximum conditions that the device can withstand without sustaining permanent damage. exce eding any of these conditions could result in permanent damage to the device. normal operation should not be expected at these conditions . in addition, expo- sure to absolute maximum rated conditions (or near absolute maximum rated conditions) for extended periods may affect device re liability. operation of the device is not guaranteed at the absolute maximum ratings, but rather at the operating conditions outlined in ? dc characteristics? on page 11 and ?ac characteristics? on page 12. operating ranges operating ranges operating ranges operating ranges vdd33 ? ? ? 3.3v i/o power for lvttl i/os n/c ? ? n/a do not connect. gnd ? i n/a ground symbol parameter min max units conditions t jmax junction temperature under bias ? 105 c t storage storage temperature ? 150 c storage temperature range ?40 85 c long term storage t solder soldering temperature ? 215 c t rework rework temperature ? 204 c table 12 absolute maximum ratings symbol parameter min typical max units conditions t j operating junction temperature range 0 ? 85 c i v15 input current for 1.5v power supply ? 800 ? ma i v18 input current for 1.8v power supply ? 1.16 ? a i v33 input current for 3.3v power supply ? 60 ? ma vdd 15 1.5v hstl supply 1.425 1.5 1.575 v 5% vdd 18 1.8v core supply 1.71 1.8 1.89 v 5% table 13 operating ranges (part 1 of 2) signal name i/o type dir. freq. remarks table 11 pll i/o (part 2 of 2)
11 of 30 march 3, 2005 idt 89TTM553 dc characteristics dc characteristics dc characteristics dc characteristics unless otherwise stated, the following parameters are provided given the conditions outlined in table 13. vdd 33 3.3v lvttl supply 3.135 3.3 3.465 v 5% vrf hstl 1 0.75v hstl reference voltage 0.7125 0.75 0.7875 v 5% power dissipation ? 3.49 3.66 w max. values use the maximum voltages and current listed in this table and typical values use the typical voltages and current. 1. this operating range applies to the following pins: bll_vref, bxt_llt_vref, fct_vref[1:0], fpt_vref[1:0], gpt_vref, ht_vref[1:0 ], and flqs_vref. symbol parameter min typical max units v ilhstl (1.5v hstl) input low voltage for 1.5v hstl inputs (vref = 0.75v) ? vref ? 0.1 v v ihhstl (1.5v hstl) input high voltage for 1.5v hstl inputs (vref = 0.75v, vddq = 1.5v) vref+ 0.1 vddq+0.3 v v il33 (3.3v lvttl) input low voltage for 3.3v lvttl inputs ? 0.8 v v ih33 (3.3v lvttl) input high voltage for 3.3v lvttl inputs 2.0 ? v v olhstl output low voltage for 1.5v hstl outputs ? 0.4 v 1.5v hstl classi w/8ma drive) v ohhstl output high voltage for 1.5v hstl outputs (vddq = 1.5v) vddq-0.4 - v 1.5v hstl classi w/ 8ma drive) v ol33 output low voltage for 3.3v cmos outputs (12ma pads) ? 0.5 v 3.3v lvttl w/ 12ma drive v oh33 output high voltage for 3.3v cmos outputs (12ma pads) 2.4 ? v 3.3v lvttl w/ 12ma drive i ilhstl (1.5v hstl) input leakage low current for 1.5v hstl inputs -10 10 ua i ihhstl (1.5v hstl) input leakage high current for 1.5v hstl inputs -10 10 ua i il33 (3.3v pads w/o pull up/down) input leakage low current for 3.3v inputs -10 10 ua i ih33 (3.3v pads w/o pull up/down) input leakage high current for 3.3v inputs -10 10 ua i il33pu (3.3v pads w/ pull up) input leakage low current for 3.3v with pull- up inputs -200 -10 ua table 14 dc parameters (part 1 of 2) symbol parameter min typical max units conditions table 13 operating ranges (part 2 of 2)
12 of 30 march 3, 2005 idt 89TTM553 a a a ac characteristics c characteristics c characteristics c characteristics unless otherwise stated, the following parameters are provided given the conditions outlined in table 13. i ih33pu (3.3v pads w/ pull up) input leakage high current for 3.3v with pull- up inputs -10 +10 ua i il33pd (3.3v pads w/ pull down) input leakage low current for 3.3v with pull- down inputs -10 +10 ua i ih33pd (3.3v pads w/ pull down) input leakage high current for 3.3v with pull- down inputs 10 200 ua symbol parameter min typical max units f sys frequency for system (core) clock reference ? 100 ? mhz t jsys jitter requirements for system clock ? ? 80 ps d sys percentage duty for system clock 45 50 55 % f zb frequency for zbus clock 33 33 66 mhz d zb percentage duty for zbus clock 45 50 55 % table 15 system clock timing symbol parameter min typical max units t kqov k/k rising edge to address/data output valid ? ? 1.6 1 1. the parameter is specified at 89ttm55x core clock frequency of 175 mhz. ns t kqox k/k rising edge to address/data output invalid 0.8 1 ?? ns t cqis c/c rising edge to data input setup ?0.2 ? ? ns t cqih c/c rising edge to data input hold ? ? 1.6 ns table 16 qdr ssram interface timing symbol parameter min typical max units t kqv zbus clock high to output valid ? ? 8.3 ns t kqx zbus clock high to output invalid 2.5 ? ? ns t kqlz zbus clock high to output low-z 1.0 ? 6.0 ns t kqhz zbus clock high to output high-z 1.0 ? 6.0 ns t s input setup time from system clock 3.0 ? ? ns t h input hold time from system clock 0 ? ? ns table 17 zbus interface timing symbol parameter min typical max units table 14 dc parameters (part 2 of 2)
13 of 30 march 3, 2005 idt 89TTM553 ac test conditions ac test conditions ac test conditions ac test conditions figure 1 ac test load 89TTM553 thermal consideration 89TTM553 thermal consideration 89TTM553 thermal consideration 89TTM553 thermal considerations s s s this section describes the temperature and heat sink calculations for flip-chip bga devices. the thermal circuit is as shown below. figure 2 89TTM553 thermal circuit input rise/fall time 1 v / ns (20% / 80%) output timing measurement reference level (v ref ) for 3.3v interfaces (vddq/2) v output load as shown in figure 1 table 18 ac test conditions symbol parameter value units conditions ? ja thermal resistance, junction to ambient (no heat sink) 9.8 c / w max: still air. 7.8 c / w typical: 200 fpm. ? jb estimated thermal resistance, junction to board 3.1 c / w ? jc thermal resistance, junction to case 0.7 c / w table 19 89TTM553 thermal characteristics z0 = 50 ? 50 ? 5 pf v ref 75 ? 75 ? vdd 20 pf for enable/disable spec for output timing ? jb t a w2 (dissipated through board) t j total power = w t a w1 ? jc ? ca device
14 of 30 march 3, 2005 idt 89TTM553 for flip-chip bga devices, there are two paths for heat dissipation: one through the package balls to the board and other throu gh the package case to air. the device specifications provide ? jb and ? jc numbers. the ? ca number comes from the heat sink manufacturer and depends on type of heat sink (area, height, fin type, etc.) and the airflow across the heat sink. the device specifications also provide the maximum op erating junction tempera- ture (t j ) that will not degrade the device reliability. the system designer should ensure that the device maximum junction temperature is not exceeded under any operating condition. one method of accomplishing this is to calculate the maximum ambient temperature (t a ) that can be tolerated based on the above device parameters. the formula is shown below. ? jb x ( ? jc + ? ca ) t a = t j - w x ----------------------- ? jb + ? jc + ? ca the following graph depicts the ambient temperature (t a ) versus ? ca. figure 3 89TTM553 ambient temperature curve for system designers, specification of the maximum device junction temperature (operating) is critical, since it allows them to select a heat sink that meets the maximum ambient temperature requirements of their system. the other parameter that is device package-specific is ? ja , without a heat sink, and is specified for various air-flow conditions. this is the intrinsic thermal resistance of the package (junction to case + case to ambient) and is mainly specified as a reference parameter. (this is when a heat sink is not present and the top surface of the package is essentially acting as the heat sink). however, in devices that have high powe r dissipation, heat sink usage is highly desirable. consequently, system designers may have limited use for this parameter. ambient temp. vs ? ca 81.0 79.7 78.8 78.2 77.7 77.2 76.9 76.6 30.0 40.0 50.0 60.0 70.0 80.0 90.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 ? ca o c/w t a o c
15 of 30 march 3, 2005 idt 89TTM553 89TTM553 reset sequence 89TTM553 reset sequence 89TTM553 reset sequence 89TTM553 reset sequence a pll reset sequence must be followed when resetting the 89TTM553 to ensure that clocks are stable when the chip comes out of r eset. this section describes the reset sequence for the 89TTM553 device. the 89TTM553 uses data presented on the zbus data and parity pins to determine the clock frequencies when the chip is in reset. the pll_cfg_ovr pin controls this feature. when left high, the pll will determine its clock frequency by sampling these values on t he zbus pins. the feature is not necessary if the default clock frequencies are desired. (the default frequency for the core clock is 133 mhz whe n a 100 mhz clock refer- ence is used.) when default frequencies are desired, the pll_cfg_ovr should be held low and it is not necessary to drive the zb us data and parity lines during the reset. core core core core p p p pll frequency setting ll frequency setting ll frequency setting ll frequency setting following is the summary of the reset sequence: 1. assert chip reset. 2. drive lor (latch on reset) values on zbus (described below) and enable configuration override on all plls. (configuration ov erride remains on forever). 3. reset plls. 4. release reset on plls. 5. release chip reset. 6. release lor value on zbus. the following values must be driven on zbus_ad[ ] and zbus_prty before the reset sequences in order to set the chip operation f requency properly. note that the setting is based on a 100mhz reference input clock (pll_sys_refclk pin). zb_prty[1:0] = 0x3, must be driven ?low? for the entire reset sequence cycles zb_ad[31:16], and zb_ad[15:0] = bits are set as: core/system clock frequency 0x154f = 187.50mhz 0x1527 = 175.00mhz 0x153a = 166.67mhz 0x1526 = 150.00mhz 0x1538 = 133.33mhz 0x1525 = 125.00mhz
16 of 30 march 3, 2005 idt 89TTM553 reset sequence timing diagram reset sequence timing diagram reset sequence timing diagram reset sequence timing diagram figure 4 89TTM553 reset sequence timing diagram pin list i/o description pin list i/o description pin list i/o description pin list i/o description the 89TTM553 pin list on page 17 uses the following i/o notations: i input o output b bidirectional ppower power reset_n zbus_ad[ ], zbus_prty[ ] pll_cfg_ovr pll_rst 10ms note: - zbus_ad[ ] and zbus_prty[ ] are used to configure the chip operating frequency, and is t 2 t 3 t 4 t 0 t 1 10ms 10ms 10ms t 5 10ms listed on next page
17 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice 8 8 8 89TTM553 pin list 9ttm553 pin list 9ttm553 pin list 9ttm553 pin list pin signal type a2 gnd p a3 vdd15 p a4 ht_clk_cn i a5 ht_clk_cp i a6 ht_din_19 i a7 ht_din_20 i a8 vdd15 p a9 gnd p a10 ht_din_34 i a11 ht_din_35 i a12 ht_dout_14 o a13 ht_dout_15 o a14 vdd15 p a15 gnd p a16 ht_dout_16 o a17 ht_dout_31 o a18 ht_dout_35 o a19 ht_addr_14 o a20 gnd p a21 vdd15 p a22 ht_addr_16 o a23 ht_addr_17 o a24 fct_addr_12 o a25 fct_addr_13 o a26 gnd p a27 vdd15 p a28 fct_dout_02 o a29 fct_dout_03 o a30 fct_dout_04 o a31 fct_dout_05 o a32 vdd15 p a33 gnd p b1 gnd p b2 gnd p b3 vdd15 p b4 ht_din_13 i b5 ht_din_14 i b6 ht_din_15 i b7 ht_din_16 i b8 vdd15 p b9 gnd p b10 ht_din_33 i pin signal type b11 ht_din_32 i b12 ht_dout_13 o b13 ht_dout_12 o b14 vdd15 p b15 gnd p b16 ht_dout_17 o b17 ht_clk_kp o b18 ht_dout_34 o b19 ht_addr_15 o b20 gnd p b21 vdd15 p b22 ht_addr_18 o b23 ht_addr_19 o b24 fct_addr_17 o b25 fct_addr_16 o b26 gnd p b27 vdd15 p b28 fct_dout_09 o b29 fct_dout_08 o b30 fct_dout_10 o b31 fct_dout_11 o b32 vdd15 p b33 gnd p b34 gnd p c1 vdd15 p c2 vdd15 p c3 ht_din_03 i c4 ht_din_08 i c5 ht_din_09 i c6 ht_din_12 i c7 ht_din_11 i c8 vdd15 p c9 gnd p c10 ht_din_28 i c11 ht_din_29 i c12 ht_dout_08 o c13 ht_dout_09 o c14 vdd15 p c15 gnd p c16 ht_dout_21 o c17 ht_clk_kn o c18 ht_addr_00 o c19 ht_addr_11 o
18 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type c20 gnd p c21 vdd15 p c22 fct_addr_01 o c23 fct_addr_00 o c24 fct_addr_18 o c25 fct_addr_19 o c26 gnd p c27 vdd15 p c28 fct_dout_12 o c29 fct_dout_13 o c30 fct_dout_17 o c31 fct_dout_16 o c32 fct_dout_22 o c33 vdd15 p c34 vdd15 p d1 bll_din_03 i d2 bll_clk_cp i d3 bll_din_11 i d4 ht_din_02 i d5 ht_din_04 i d6 ht_din_06 i d7 ht_din_07 i d8 vdd15 p d9 gnd p d10 ht_din_26 i d11 ht_din_27 i d12 ht_dout_06 o d13 ht_dout_07 o d14 vdd15 p d15 gnd p d16 ht_dout_20 o d17 ht_dout_30 o d18 ht_addr_01 o d19 ht_addr_10 o d20 gnd p d21 vdd15 p d22 fct_addr_02 o d23 fct_addr_03 o d24 fct_clk_kn o d25 fct_clk_kp o d26 gnd p d27 vdd15 p d28 fct_dout_18 o pin signal type d29 fct_dout_19 o d30 fct_dout_20 o d31 fct_dout_23 o d32 fct_din_05 i d33 fct_din_10 i d34 fct_clk_cp i e1 bll_din_04 i e2 bll_clk_cn i e3 bll_din_10 i e4 bll_din_15 i e5 bll_din_14 i e6 ht_din_05 i e7 ht_din_10 i e8 vdd15 p e9 gnd p e10 ht_vref_01 p e11 ht_din_25 i e12 ht_dout_05 o e13 ht_dout_04 o e14 vdd15 p e15 gnd p e16 ht_dout_22 o e17 ht_dout_28 o e18 ht_addr_02 o e19 ht_addr_09 o e20 gnd p e21 vdd15 p e22 fct_addr_04 o e23 fct_addr_05 o e24 fct_dout_01 o e25 fct_dout_00 o e26 gnd p e27 vdd15 p e28 fct_din_08 i e29 fct_dout_21 o e30 fct_din_01 i e31 fct_din_00 i e32 fct_din_04 i e33 fct_din_09 i e34 fct_clk_cn i f1 bll_din_00 i f2 bll_din_06 i f3 bll_din_08 i
19 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type f4 bll_din_12 i f5 bll_din_16 i f6 ht_din_00 i f7 ht_vref_00 p f8 vdd15 p f9 gnd p f10 ht_din_21 i f11 ht_din_22 i f12 ht_dout_00 o f13 ht_dout_01 o f14 vdd15 p f15 gnd p f16 ht_dout_23 o f17 ht_dout_29 o f18 ht_addr_03 o f19 ht_addr_08 o f20 gnd p f21 vdd15 p f22 fct_addr_09 o f23 fct_addr_08 o f24 fct_addr_15 o f25 fct_addr_14 o f26 gnd p f27 vdd15 p f28 fct_vref_00 p f29 fct_dout_25 o f30 fct_dout_27 o f31 fct_din_02 i f32 fct_din_06 i f33 fct_din_11 i f34 fct_din_16 i g1 bll_dout_17 o g2 bll_din_05 i g3 bll_din_09 i g4 bll_din_13 i g5 bll_din_17 i g6 ht_din_01 i g7 vdd15 p g8 vdd15 p g9 gnd p g10 ht_din_31 i g11 ht_din_30 i g12 ht_dout_19 o pin signal type g13 ht_dout_18 o g14 vdd15 p g15 gnd p g16 ht_dout_24 o g17 ht_dout_25 o g18 ht_addr_07 o g19 ht_addr_06 o g20 gnd p g21 vdd15 p g22 fct_addr_10 o g23 fct_addr_11 o g24 fct_wr_n o g25 fct_rd_n o g26 gnd p g27 vdd15 p g28 vdd15 p g29 fct_dout_24 o g30 fct_dout_26 o g31 fct_din_03 i g32 fct_din_07 i g33 fct_din_12 i g34 fct_din_15 i h1 vdd15 p h2 vdd15 p h3 vdd15 p h4 vdd15 p h5 vdd15 p h6 vdd15 p h7 vdd15 p h8 gnd p h9 bll_din_07 i h10 ht_din_24 i h11 ht_din_23 i h12 ht_dout_11 o h13 ht_dout_10 o h14 vdd15 p h15 gnd p h16 ht_dout_33 o h17 ht_dout_32 o h18 ht_addr_04 o h19 ht_addr_13 o h20 gnd p h21 vdd15 p
20 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type h22 ht_wr_n o h23 ht_rd_n o h24 fct_dout_07 o h25 fct_dout_06 o h26 gnd p h27 gnd p h28 vdd15 p h29 vdd15 p h30 vdd15 p h31 vdd15 p h32 vdd15 p h33 vdd15 p h34 vdd15 p j1 gnd p j2 gnd p j3 gnd p j4 gnd p j5 gnd p j6 gnd p j7 gnd p j8 gnd p j9 bll_vref p j10 ht_din_18 i j11 ht_din_17 i j12 ht_dout_03 o j13 ht_dout_02 o j14 vdd15 p j15 gnd p j16 ht_dout_27 o j17 ht_dout_26 o j18 ht_addr_05 o j19 ht_addr_12 o j20 gnd p j21 vdd15 p j22 fct_addr_07 o j23 fct_addr_06 o j24 fct_dout_15 o j25 fct_dout_14 o j26 fct_din_14 i j27 fct_din_13 i j28 gnd p j29 gnd p j30 gnd p pin signal type j31 gnd p j32 gnd p j33 gnd p j34 gnd p k1 bll_dout_02 o k2 bll_dout_05 o k3 bll_dout_08 o k4 bll_dout_10 o k5 bll_dout_13 o k6 bll_dout_16 o k7 bll_dout_03 o k8 bll_dout_11 o k9 bll_din_01 i k26 fct_din_21 i k27 flqs_dout_prty o k28 fct_din_17 i k29 fct_din_19 i k30 fct_vref_01 p k31 fct_din_24 i k32 fct_din_26 i k33 flqs_dout_01 o k34 flqs_dout_02 o l1 bll_dout_01 o l2 bll_dout_06 o l3 bll_dout_07 o l4 bll_dout_09 o l5 bll_dout_14 o l6 bll_dout_15 o l7 bll_dout_04 o l8 bll_dout_12 o l9 bll_din_02 i l26 fct_din_22 i l27 flqs_tic_out o l28 fct_din_18 i l29 fct_din_20 i l30 fct_din_23 i l31 fct_din_25 i l32 fct_din_27 i l33 flqs_dout_00 o l34 flqs_dout_03 o m1 bll_addr_13 o m2 bll_addr_15 o m3 bll_addr_18 o
21 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type m4 bll_clk_kp o m5 bll_addr_21 o m6 bll_addr_02 o m7 bll_dout_00 o m8 bll_addr_01 o m9 bll_addr_00 o m26 flqs_dout_06 o m27 flqs_dout_13 o m28 flqs_tic_in i m29 flqs_dout_04 o m30 flqs_dout_09 o m31 flqs_clkout o m32 flqs_dout_11 o m33 flqs_dout_16 o m34 flqs_dout_17 o n1 bll_addr_12 o n2 bll_addr_14 o n3 bll_addr_19 o n4 bll_clk_kn o n5 bll_addr_20 o n6 bll_rd_n o n7 bll_wr_n o n8 bll_addr_17 o n9 bll_addr_16 o n26 flqs_dout_07 o n27 flqs_dout_14 o n28 flqs_din_14 i n29 flqs_dout_05 o n30 flqs_dout_08 o n31 flqs_dout_10 o n32 flqs_dout_12 o n33 flqs_dout_15 o n34 flqs_dout_18 o p1 vdd15 p p2 vdd15 p p3 vdd15 p p4 vdd15 p p5 vdd15 p p6 vdd15 p p7 vdd15 p p8 vdd15 p p9 vdd15 p p14 gnd p pin signal type p15 vdd18 p p16 gnd p p17 vdd18 p p18 gnd p p19 vdd18 p p20 gnd p p21 vdd18 p p26 vdd15 p p27 vdd15 p p28 vdd15 p p29 vdd15 p p30 vdd15 p p31 vdd15 p p32 vdd15 p p33 vdd15 p p34 vdd15 p r1 gnd p r2 gnd p r3 gnd p r4 gnd p r5 gnd p r6 gnd p r7 gnd p r8 gnd p r9 gnd p r14 vdd18 p r15 gnd p r16 vdd18 p r17 gnd p r18 vdd18 p r19 gnd p r20 vdd18 p r21 gnd p r26 gnd p r27 gnd p r28 gnd p r29 gnd p r30 gnd p r31 gnd p r32 gnd p r33 gnd p r34 gnd p t1 bll_addr_10 o
22 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type t2 bll_addr_11 o t3 bll_addr_07 o t4 bll_addr_06 o t5 bll_addr_05 o t6 bll_addr_04 o t7 bxt_wr_n o t8 bll_addr_09 o t9 bll_addr_08 o t14 gnd p t15 vdd18 p t16 gnd p t17 vdd18 p t18 gnd p t19 vdd18 p t20 gnd p t21 vdd18 p t26 flqs_vref p t27 flqs_din_01 i t28 flqs_din_09 i t29 flqs_din_10 i t30 flqs_din_11 i t31 flqs_din_13 i t32 flqs_din_12 i t33 flqs_din_prty i t34 flqs_dout_19 o u1 bxt_addr_19 o u2 bxt_addr_18 o u3 bxt_addr_20 o u4 bxt_addr_21 o u5 bxt_addr_00 o u6 bxt_addr_01 o u7 bll_addr_03 o u8 bxt_rd_n o u9 bxt_addr_02 o u14 vdd18 p u15 gnd p u16 vdd18 p u17 gnd p u18 vdd18 p u19 gnd p u20 vdd18 p u21 gnd p u26 flqs_din_07 i pin signal type u27 flqs_din_00 i u28 flqs_din_08 i u29 flqs_din_06 i u30 flqs_clkin i u31 flqs_din_05 i u32 flqs_din_04 i u33 flqs_din_03 i u34 flqs_din_02 i v1 bxt_addr_15 o v2 bxt_clk_kp o v3 bxt_clk_kn o v4 bxt_addr_14 o v5 bxt_addr_12 o v6 bxt_addr_13 o v7 bxt_addr_09 o v8 bxt_addr_17 o v9 bxt_addr_11 o v14 gnd p v15 vdd18 p v16 gnd p v17 vdd18 p v18 gnd p v19 vdd18 p v20 gnd p v21 vdd18 p v26 tdo o v27 tms i v28 pll_2x_bpclk i v29 tdi i v30 tck i v31 reserve_0 i v32 scan_en i v33 iddq i v34 reserve_1 i w1 bxt_dout_01 o w2 bxt_dout_02 o w3 bxt_addr_05 o w4 bxt_addr_04 o w5 bxt_addr_06 o w6 bxt_addr_07 o w7 bxt_addr_08 o w8 bxt_addr_16 o w9 bxt_addr_10 o
23 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type w14 vdd18 p w15 gnd p w16 vdd18 p w17 gnd p w18 vdd18 p w19 gnd p w20 vdd18 p w21 gnd p w26 reset_n i w27 pll_sys_refclk i w28 trst_n i w29 pll_bp_mode i w30 pll_mon o w31 pll_cfg_ovr i w32 pll_rst i w33 nc w34 pll_vssa i y1 gnd p y2 gnd p y3 gnd p y4 gnd p y5 gnd p y6 gnd p y7 gnd p y8 gnd p y9 gnd p y14 gnd p y15 vdd18 p y16 gnd p y17 vdd18 p y18 gnd p y19 vdd18 p y20 gnd p y21 vdd18 p y26 gnd p y27 gnd p y28 gnd p y29 gnd p y30 gnd p y31 gnd p y32 gnd p y33 gnd p y34 gnd p pin signal type aa1 vdd15 p aa2 vdd15 p aa3 vdd15 p aa4 vdd15 p aa5 vdd15 p aa6 vdd15 p aa7 vdd15 p aa8 vdd15 p aa9 vdd15 p aa14 vdd18 p aa15 gnd p aa16 vdd18 p aa17 gnd p aa18 vdd18 p aa19 gnd p aa20 vdd18 p aa21 gnd p aa26 vdd33 p aa27 vdd33 p aa28 vdd33 p aa29 vdd33 p aa30 vdd33 p aa31 vdd33 p aa32 vdd33 p aa33 vdd33 p aa34 vdd33 p ab1 bxt_dout_00 o ab2 bxt_clk_cp i ab3 bxt_din_00 i ab4 llt_din_09 i ab5 llt_din_06 i ab6 llt_din_04 i ab7 bxt_addr_03 o ab8 bxt_din_02 i ab9 bxt_llt_vref p ab26 zbus_ad_00 b ab27 zbus_ad_01 b ab28 zbus_ad_12 b ab29 zbus_ad_11 b ab30 zbus_ad_06 b ab31 zbus_ad_04 b ab32 zbus_ad_03 b ab33 zbus_avalid_n b
24 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type ab34 pll_vdda i ac1 bxt_din_03 i ac2 bxt_clk_cn i ac3 llt_din_10 i ac4 llt_din_08 i ac5 llt_din_07 i ac6 llt_din_03 i ac7 bxt_dout_03 o ac8 bxt_din_01 i ac9 llt_din_05 i ac26 zbus_ad_08 b ac27 zbus_ad_09 b ac28 zbus_ad_13 b ac29 zbus_ad_10 b ac30 zbus_ad_07 b ac31 zbus_ad_05 b ac32 zbus_ad_02 b ac33 zbus_clk i ac34 nc ad1 llt_clk_cp i ad2 llt_din_01 i ad3 llt_dout_09 o ad4 llt_dout_07 o ad5 llt_dout_04 o ad6 llt_dout_01 o ad7 llt_wr_n o ad8 llt_din_00 i ad9 llt_dout_03 o ad26 gpt_din_02 i ad27 zbus_int_n_01 o ad28 zbus_devid_01 i ad29 zbus_prty b ad30 vdd33 p ad31 zbus_dvalid_n b ad32 vdd33 p ad33 zbus_devid_03 i ad34 zbus_ad_14 b ae1 llt_clk_cn i ae2 llt_din_02 i ae3 llt_dout_08 o ae4 llt_dout_06 o ae5 llt_dout_05 o ae6 llt_dout_00 o pin signal type ae7 llt_rd_n o ae8 llt_dout_10 o ae9 llt_dout_02 o ae26 gpt_din_01 i ae27 zbus_int_n_00 o ae28 zbus_devid_00 i ae29 zbus_dir o ae30 zbus_int_n_02 o ae31 zbus_gnt_n i ae32 zbus_devid_04 i ae33 zbus_devid_02 i ae34 zbus_ad_15 b af1 gnd p af2 gnd p af3 gnd p af4 gnd p af5 gnd p af6 gnd p af7 gnd p af8 llt_addr_16 o af9 llt_addr_17 o af10 fpt_din_25 i af11 fpt_din_26 i af12 fpt_bw_n_01 o af13 fpt_bw_n_02 o af14 vdd15 p af15 gnd p af16 fpt_addr_07 o af17 fpt_addr_00 o af18 fpt_dout_21 o af19 fpt_dout_22 o af20 gnd p af21 vdd15 p af22 gpt_bw_n_00 o af23 gpt_bw_n_01 o af24 gpt_addr_00 o af25 gpt_addr_01 o af26 gpt_vref p af27 gnd p af28 gnd p af29 gnd p af30 gnd p af31 gnd p
25 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type af32 gnd p af33 gnd p af34 gnd p ag1 vdd15 p ag2 vdd15 p ag3 vdd15 p ag4 vdd15 p ag5 vdd15 p ag6 vdd15 p ag7 vdd15 p ag8 gnd p ag9 gnd p ag10 fpt_din_17 i ag11 fpt_din_18 i ag12 fpt_addr_15 o ag13 fpt_addr_16 o ag14 vdd15 p ag15 gnd p ag16 fpt_addr_08 o ag17 fpt_dout_35 o ag18 fpt_dout_29 o ag19 fpt_dout_30 o ag20 gnd p ag21 vdd15 p ag22 fpt_dout_05 o ag23 fpt_dout_06 o ag24 gpt_addr_08 o ag25 gpt_addr_09 o ag26 gpt_din_07 i ag27 gnd p ag28 vdd15 p ag29 vdd15 p ag30 vdd15 p ag31 vdd15 p ag32 vdd15 p ag33 vdd15 p ag34 vdd15 p ah1 llt_addr_18 o ah2 llt_addr_13 o ah3 llt_addr_07 o ah4 llt_clk_kp o ah5 llt_addr_00 o ah6 fpt_din_34 i pin signal type ah7 vdd15 p ah8 vdd15 p ah9 gnd p ah10 fpt_din_11 i ah11 fpt_din_12 i ah12 fpt_din_01 i ah13 fpt_din_00 i ah14 vdd15 p ah15 gnd p ah16 fpt_addr_01 o ah17 fpt_addr_02 o ah18 fpt_dout_20 o ah19 fpt_dout_19 o ah20 gnd p ah21 vdd15 p ah22 fpt_dout_13 o ah23 fpt_dout_14 o ah24 gpt_addr_14 o ah25 gpt_addr_15 o ah26 gnd p ah27 vdd15 p ah28 vdd15 p ah29 gpt_dout_01 o ah30 gpt_din_17 i ah31 gpt_din_13 i ah32 gpt_din_09 i ah33 gpt_din_05 i ah34 zbus_req_n o aj1 llt_addr_19 o aj2 llt_addr_12 o aj3 llt_addr_06 o aj4 llt_clk_kn o aj5 llt_addr_01 o aj6 fpt_din_35 i aj7 llt_addr_09 o aj8 vdd15 p aj9 gnd p aj10 fpt_din_04 i aj11 fpt_din_05 i aj12 fpt_bw_n_03 o aj13 fpt_wr_n o aj14 vdd15 p aj15 gnd p
26 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type aj16 fpt_addr_03 o aj17 fpt_dout_34 o aj18 fpt_dout_24 o aj19 fpt_dout_18 o aj20 gnd p aj21 vdd15 p aj22 gpt_rd_n o aj23 gpt_addr_20 o aj24 gpt_addr_07 o aj25 gpt_addr_06 o aj26 gnd p aj27 vdd15 p aj28 gpt_dout_10 o aj29 gpt_dout_00 o aj30 gpt_din_16 i aj31 gpt_din_12 i aj32 gpt_din_08 i aj33 gpt_din_06 i aj34 gpt_din_00 i ak1 llt_addr_15 o ak2 llt_addr_10 o ak3 llt_addr_04 o ak4 llt_addr_02 o ak5 llt_addr_03 o ak6 fpt_din_31 i ak7 llt_addr_08 o ak8 vdd15 p ak9 gnd p ak10 fpt_din_13 i ak11 fpt_din_14 i ak12 fpt_bw_n_00 o ak13 fpt_rd_n o ak14 vdd15 p ak15 gnd p ak16 fpt_addr_04 o ak17 fpt_dout_33 o ak18 fpt_dout_23 o ak19 fpt_dout_17 o ak20 gnd p ak21 vdd15 p ak22 gpt_wr_n o ak23 fpt_dout_00 o ak24 gpt_addr_10 o pin signal type ak25 gpt_addr_11 o ak26 gnd p ak27 vdd15 p ak28 gpt_dout_11 o ak29 gpt_dout_05 o ak30 gpt_din_14 i ak31 gpt_din_15 i ak32 gpt_din_10 i ak33 gpt_clk_cn i ak34 gpt_din_04 i al1 llt_addr_14 o al2 llt_addr_11 o al3 llt_addr_05 o al4 fpt_din_33 i al5 fpt_din_30 i al6 fpt_din_29 i al7 fpt_vref_01 p al8 vdd15 p al9 gnd p al10 fpt_vref_00 p al11 fpt_din_10 i al12 fpt_addr_20 o al13 fpt_addr_19 o al14 vdd15 p al15 gnd p al16 fpt_addr_05 o al17 fpt_dout_32 o al18 fpt_dout_25 o al19 fpt_dout_15 o al20 gnd p al21 vdd15 p al22 fpt_dout_02 o al23 fpt_dout_01 o al24 gpt_clk_kp o al25 gpt_clk_kn o al26 gnd p al27 vdd15 p al28 gpt_dout_07 o al29 gpt_dout_06 o al30 gpt_dout_04 o al31 gpt_dout_02 o al32 gpt_din_11 i al33 gpt_clk_cp i
27 of 30 march 3, 2005 idt 89TTM553 *notice: the information in this document is subject to change without notice pin signal type al34 gpt_din_03 i am1 vdd15 p am2 vdd15 p am3 fpt_din_32 i am4 fpt_din_27 i am5 fpt_din_28 i am6 fpt_din_24 i am7 fpt_din_23 i am8 vdd15 p am9 gnd p am10 fpt_din_09 i am11 fpt_din_08 i am12 fpt_addr_17 o am13 fpt_addr_18 o am14 vdd15 p am15 gnd p am16 fpt_addr_06 o am17 fpt_dout_31 o am18 fpt_dout_26 o am19 fpt_dout_16 o am20 gnd p am21 vdd15 p am22 fpt_dout_04 o am23 fpt_dout_03 o am24 gpt_addr_13 o am25 gpt_addr_12 o am26 gnd p am27 vdd15 p am28 gpt_dout_12 o am29 gpt_dout_13 o am30 gpt_dout_09 o am31 gpt_dout_08 o am32 gpt_dout_03 o am33 vdd15 p am34 vdd15 p an1 gnd p an2 gnd p an3 vdd15 p an4 fpt_din_22 i an5 fpt_din_21 i an6 fpt_din_19 i an7 fpt_din_20 i an8 vdd15 p pin signal type an9 gnd p an10 fpt_din_06 i an11 fpt_din_07 i an12 fpt_addr_14 o an13 fpt_addr_13 o an14 vdd15 p an15 gnd p an16 fpt_addr_10 o an17 fpt_clk_kp o an18 fpt_dout_27 o an19 fpt_dout_12 o an20 gnd p an21 vdd15 p an22 fpt_dout_07 o an23 fpt_dout_08 o an24 gpt_addr_16 o an25 gpt_addr_17 o an26 gnd p an27 vdd15 p an28 gpt_dout_17 o an29 gpt_dout_16 o an30 gpt_dout_15 o an31 gpt_dout_14 o an32 vdd15 p an33 gnd p an34 gnd p ap2 gnd p ap3 vdd15 p ap4 fpt_clk_cn i ap5 fpt_clk_cp i ap6 fpt_din_16 i ap7 fpt_din_15 i ap8 vdd15 p ap9 gnd p ap10 fpt_din_03 i ap11 fpt_din_02 i ap12 fpt_addr_12 o ap13 fpt_addr_11 o ap14 vdd15 p ap15 gnd p ap16 fpt_addr_09 o ap17 fpt_clk_kn o ap18 fpt_dout_28 o
28 of 30 march 3, 2005 idt 89TTM553 pin signal type ap19 fpt_dout_11 o ap20 gnd p ap21 vdd15 p ap22 fpt_dout_10 o ap23 fpt_dout_09 o ap24 gpt_addr_19 o ap25 gpt_addr_18 o ap26 gnd p ap27 vdd15 p ap28 gpt_addr_05 o ap29 gpt_addr_04 o ap30 gpt_addr_02 o ap31 gpt_addr_03 o ap32 vdd15 p ap33 gnd p
29 of 30 march 3, 2005 idt 89TTM553 8 8 8 89TTM553 package 9ttm553 package 9ttm553 package 9ttm553 package the package is an lsi logic fpbga-hp, having 960 pins, with 1 mm pitch; a 34 34 pin array; and a 35 35 mm enclosure. figure 5 shows the package geometry. figure 5 89TTM553 package diagram
30 of 30 march 3, 2005 idt 89TTM553 corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ordering informatio ordering informatio ordering informatio ordering information n n n valid combinations valid combinations valid combinations valid combinations revision history revision history revision history revision history november 23, 2004 : initial publication by idt. january 12, 2005 : on page 14, deleted reference to lvds in the core pll frequency setting heading. march 3, 2005 : in table 11, changed frequency for pll_sys_refclk from 125 to 100 mhz. 89TTM553bl 960-pin fcbga package, commercial temperature nn aaa 55x a a operating voltage device family product package temp range t blank commercial temperature (see thermal considerations traffic manager product family 89 serial switching product 960-pin fcbga bl 552 aggregate flow device tm 1.8v 5% core voltage detail 553 per flow device switch fabric sf legend a = alpha character n = numeric character section)

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